1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a vertical transistor and a method for manufacturing the same.
2. Related Art
With increase in a degree of integration of semiconductor devices, a channel length of a transistor is reduced increasingly. The reduction in the channel length causes drain induced barrier lowering (BIDL) a hot carrier effect, and a short channel effect, such as punch-through.
To alleviate these concerns, various methods, such as a method of reducing a length of a junction region, a method of increasing a channel length by forming a recess in a channel region of the transistor, and the like are suggested.
However, as the degree of integration of semiconductor devices is approaching Giga bytes, it may be difficult to satisfy a required device area using a planar transistor structure in which junction regions are formed at both sides of gates even when the channel length is scaled down. Therefore, to alleviate this concern, vertical transistor technology is suggested.
A semiconductor device having a vertical transistor in the related art will be described with reference to FIG. 3.
The semiconductor device in the related art includes a plurality of pillars 115 extending to a vertical direction from a semiconductor substrate 110, and a gate insulating layer 130 surrounding a lateral surface of each of the pillars 115, and a gate electrode 140 surrounding each of the pillars surrounded with the gate insulating layer 130 to a predetermined height. A silicide layer 160 is formed on an upper surface of each of the pillars, and a lower electrode 170 is formed on the silicide layer 160.
A level of difficulty in a process is considerably increasing according to decrease in the size of semiconductor device having the vertical channel transistor, specifically, a phase-change random access memory (PRAM). In particular, an ON current may be reduced due to increase in a contact resistance according to decrease in size of a 20 nm-graded or less device.
Therefore, there is a need for a method for increasing an ON current due to reduction in a contact resistance in a recent semiconductor device.